Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. SE: What are some of the technologies being developed at the Innovative Devices Laboratory?Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically, our research focus is process integration, new transistor architectures and new substrate evaluations. We also focus on 3D monolithic integration. And we are looking at new materials beyond CMOS. We also have activities in sensors integrated with CMOS.SE: What are some of the challenges in IC scaling?Vinet: Litho is definitely a huge challenge. Then, for the device guys, we’ve got power and energy tradeoffs to tackle. So, we try to structure our research around the materials and design. The new materials present many challenges. For example, one of the main reasons for the introduction of high-mobility materials is to boost the performance. But when they are integrated in a transistor process, are we going to preserve the intrinsic properties and are we able to get the expected gain?SE: IBM, Leti, Soitec, ST and others are instrumental in developing FDSOI. How do you see FDSOI versus bulk finFETs?Vinet: From… Read full this story
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